Elements of Computing Systems - Chapter 3 - Understandings

Great book and I am proud to own one!

These are my understandings and summary from Chapter - 3.

Sequential Logic
  • All the Chips we have built so far were: Combinational Chips
  • Combinational Chips can not maintain state.
  • Sequential Chips can maintain state. 
The Clock
  • In computers, time is represented by a master clock
  • The current clock phase is represented by a binary signal.
  • Using the hardware circuitry, the signal is broadcast to every sequential chip in the platform.
DFF: Data Flip Flop
  • DFF consists of a single - bit data input and a single - bit data output.
  • DFF has a clock input, that continuously changes according to the Master Clock 's signal.
  • DFF outputs the input value from the previous time unit!
  • A Register is a device that can store (or remember..) a value over time.
  • Here is my 1 - Bit Register implementation in my own hand drawing:

  • The "select bit" of the Multiplexor becomes the "load bit". 
  • If load = 1, muxOut = b = in. 
  • If load = 0, muxOut = a. 
w - Bit Registers
  • 1 - Bit Register is hardly useful for us.
  • Lets pack 16 register into one chip, either load 16 of them at once or read 16 of them at once. 

  • w - Bit Register is has a w-bit bus as input (in[w]) and w-bit but as output (out[w]).  
  • It only has 1 load bit. Either 16 bits are loaded at once, or read at once. 
  • We lost the ability to load or read a 1 - Bit Register
  • The Multi - Bit Contents of Registers are referred to as: words


  • Once we have the ability to represent words, we can build memory banks, by stacking up w - Bit Register.
  • We need an additional control unit, the address bit, to address the w - Bit Register we want to load or read. 
  • Here is a nice sketch that shows a Memory unit:

I was also nice enough to draw a sketch of a 32 - Bit Memory module, that consists of 2 16 - Bit Registers.   

And finally, my implementations for the Chips that will be used for the Heck Computer:
CHIP Bit {
    IN in, load;
    OUT out;
    Mux(a=a, b=in, sel=load, out=muxOut);
    DFF(in=muxOut, out=out, out=a);
CHIP Register {
    IN in[16], load;
    OUT out[16];
    Bit(in=in[0] , load=load, out=out[0]);
    Bit(in=in[1] , load=load, out=out[1]);
    Bit(in=in[2] , load=load, out=out[2]);
    Bit(in=in[3] , load=load, out=out[3]);
    Bit(in=in[4] , load=load, out=out[4]);
    Bit(in=in[5] , load=load, out=out[5]);
    Bit(in=in[6] , load=load, out=out[6]);
    Bit(in=in[7] , load=load, out=out[7]);
    Bit(in=in[8] , load=load, out=out[8]);
    Bit(in=in[9] , load=load, out=out[9]);
    Bit(in=in[10], load=load, out=out[10]);
    Bit(in=in[11], load=load, out=out[11]);
    Bit(in=in[12], load=load, out=out[12]);
    Bit(in=in[13], load=load, out=out[13]);
    Bit(in=in[14], load=load, out=out[14]);
    Bit(in=in[15], load=load, out=out[15]);
    IN in[16], load, address[3];
    OUT out[16];
       DMux8Way(in=load, sel=address, a=ao, b=bo, c=co, d=do, e=eo, f=fo, g=go, h=ho); 
       Mux8Way16(a=aa, b=bb, c=cc, d=dd, e=ee, f=ff, g=gg, h=hh, sel=address, out=out);
    IN in[16], load, address[6];
    OUT out[16];
       DMux8Way(in=load, a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8, sel=address[3..5]);
       RAM8(in=in, load=load1, address=address[0..2], out=o1);
       RAM8(in=in, load=load2, address=address[0..2], out=o2);
       RAM8(in=in, load=load3, address=address[0..2], out=o3);
       RAM8(in=in, load=load4, address=address[0..2], out=o4);
       RAM8(in=in, load=load5, address=address[0..2], out=o5);
       RAM8(in=in, load=load6, address=address[0..2], out=o6);
       RAM8(in=in, load=load7, address=address[0..2], out=o7);
       RAM8(in=in, load=load8, address=address[0..2], out=o8);
       Mux8Way16(out=out, a=o1, b=o2, c=o3, d=o4, e=o5, f=o6, g=o7, h=o8, sel=address[3..5]);
    IN in[16], load, address[12];
    OUT out[16];
 DMux8Way(in=load, sel=address[9..11], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
 RAM512(in=in, load=loada, address=address[0..8], out=outa);
 RAM512(in=in, load=loadb, address=address[0..8], out=outb);
 RAM512(in=in, load=loadc, address=address[0..8], out=outc);
 RAM512(in=in, load=loadd, address=address[0..8], out=outd);
 RAM512(in=in, load=loade, address=address[0..8], out=oute);
 RAM512(in=in, load=loadf, address=address[0..8], out=outf);
 RAM512(in=in, load=loadg, address=address[0..8], out=outg);
 RAM512(in=in, load=loadh, address=address[0..8], out=outh);
 Mux8Way16(a=outa, b=outb, c=outc, d=outd, e=oute, f=outf, g=outg, h=outh, sel=address[9..11], out=out); 
    IN in[16], load, address[9];
    OUT out[16];
 DMux8Way(in=load, sel=address[6..8], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
 RAM64(in=in, load=loada, address=address[0..5], out=outa);
 RAM64(in=in, load=loadb, address=address[0..5], out=outb);
 RAM64(in=in, load=loadc, address=address[0..5], out=outc);
 RAM64(in=in, load=loadd, address=address[0..5], out=outd);
 RAM64(in=in, load=loade, address=address[0..5], out=oute);
 RAM64(in=in, load=loadf, address=address[0..5], out=outf);
 RAM64(in=in, load=loadg, address=address[0..5], out=outg);
 RAM64(in=in, load=loadh, address=address[0..5], out=outh);
 Mux8Way16(a=outa, b=outb, c=outc, d=outd, e=oute, f=outf, g=outg, h=outh, sel=address[6..8], out=out); 
    IN in[16], load, address[14];
    OUT out[16];
 DMux4Way(in=load, sel=address[12..13], a=loada, b=loadb, c=loadc, d=loadd);
 RAM4K(in=in, load=loada, address=address[0..11], out=outa);
 RAM4K(in=in, load=loadb, address=address[0..11], out=outb);
 RAM4K(in=in, load=loadc, address=address[0..11], out=outc);
 RAM4K(in=in, load=loadd, address=address[0..11], out=outd);
 Mux4Way16(a=outa, b=outb, c=outc, d=outd, sel=address[12..13], out=out);