Building the Hack Computer Hardware in Logisim - Part - 3

..and my notes...

Ok so in Part - 2 we have shown the Flip Flops. Lets summarise these Flip Flops, before we move on:

R - S Flip Flop:


Level Triggered Flip Flop:

Edge Triggered Flip Flop:

Master - Slave Flip Flop:

Now we will move on to building Registers.

For building the Registers, we will be using the Flip Flops we have built already.

We will need 2 types of Registers: Master - Slave Registers and Edge - Triggered Registers

For both types, we will first build 1-Bit versions, then move on to 16-Bit versions.

Let 's start with 1-Bit Master Slave Register:
Here is the circuit diagram:

So what are the properties of a Master Slave Register?

While the clock == 1
----while store == 1
--------store whatever is in data..

While clock == 0
----output whatever you stored... 

So here I am testing the 1-Bit Master Slave Register:



However we actually want a different functionality.. We want the data to be stored only at the instant clock goes from low to high.. So we will combine an Edge Triggered Flip Flop with a Master Slave Flip Flop and we will create an Edge Triggered Master Slave Register:

Let 's test this 1-Bit Edge Triggered Master Slave Register:



We can easily construct 16-Bit versions of these Registers:
16-Bit Master - Slave Register:

16-Bit Edge Triggered Master - Slave Register:

Lets test this 16-Bit Edge Triggered Master Slave Register in isolation:



Now that we have our Registers, we might as well stack them up and have RAMs...

Here is how I implemented the RAM8:

Now we have 3 bits for address. This makes us select a 16-Bit Register in the stack. 

Lets test our RAM8 in isolation:




What we can do at this point actually is, we can further stack up RAM8 's to create a RAM64

However, Logism will not be able to process this. So we have to use the built - in RAM64. But we will need to modify it a little so that it acts as a Level Triggered RAM 64

The only difference between RAM8 and RAM64 is, actually the Address length available.. 

You can think it like this. We have 8 boxes of RAM8s..

First 3 bits in the address picks which box we pick.. 
Last 3 bits will pick which of the RAM8 's in the selected box we load (or read).

Here is our RAM64 in test:

 
Actually at this point, creating the RAM32K or RAM64K is not very much different..

You just keep stacking up the RAMs you have built, until you have 15(for 32K) or 16 Bits((for 64K) for address.

Let 's consider the 64K Memory..

Each Register we have is 16 - Bits
We have 16 Bits for Address as well, which means 65536 addresses (hence the 64K..)..  
At each address we can store 16 bits, which means 1048576 bits in total.. Divide by 131072 bytes.

So at this point it should be clear how a 16 bit, word addressable (our RAM is NOT byte-addressable, we can not address individual bytes, we can address 16-bits at once, hence word addressable..) RAM.

I will stop at this point. 

We already have:
ALU
Registers 
RAM 

What is missing is:
Counter
Something that will tell us whether we are in Fetch or Execute cycle..